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TECHNICAL DATA Quard Uart with 256-Byte FIFO
1. Functional Description
IN16C1054 is a quad UART(Universal Asynchronous Receiver/Transmitter) with 256-byte FIFO supporting maximum communication speed of 5.3Mbps. It offers flow control function by hardware or software and signal lines which can open or close the Tx/Rx input/output when communicating by RS-422 or RS-485. It can handle four interrupt signals (INT0, INT1, INT2 and INT3) with one global interrupt signal line (GINT) and offers a new `Xoff re-transmit' function in addition to Xon any character. UART can convert 8-bit parallel data to asynchronous serial data and vice versa. It can transmit 5 to 8-bit letters, program I/O interrupt trigger level and has 256-byte I/O data FIFO. UART can generate any baud rate using clock and programmable divisor, transmit data with even, odd or no parity and 1, 1.5, 2 stop bit, and detect break, idle, framing error, FIFO overflow and parity error in input data. UART has a software interface for modem controlling. IN16C1054 offers TQFP80 and PLCC68 packages.
IN16C1054
2. Features
* * * * * * * * * * * *
4 Channel UART 3.3V Operation 5V Tolerant Inputs Pin-to-pin Compatible with Industry Standard SB16C554 with Additional Enhancements Up to 5.3 Mbps Baud Rate (Up to 85 MHz Oscillator Input Clock) 256-byte Transmit FIFO 256-byte Receive FIFO with Error Flags Industrial Temperature Range (-20 to +85 ) Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation Software (Xon/Xoff) / Hardware (RTS#/CTS#) Flow Control Programmable Xon/Xoff Characters Programmable Auto-RTS and Auto-CTS
* * * * * * * * *
Optional Data Flow Additional Halt by Xoff Retransmit Control RS-422 Point to Point/Multi-Drop Control RS-485 Echo/Non Echo Control DMA Signaling Capability for Both Received and Transmitted Data Software Selectable Baud Rate Generator Prescaler Provides Additional Divide-by-4 Function Fast Data Bus Access Time Programmable Sleep Mode Programmable Serial Interface Characteristics 5, 6, 7, or 8-bit Characters Even, Odd, or No Parity Bit Generation and Detection 1, 1.5, or 2 Stop Bit Generation
* * * *
False Start Bit Detection Line Break Generation and Detection Fully Prioritized Interrupt System Controls Modem Control Functions (RTS#, CTS#, DTR#, DSR#, DCD#, and RI#)
* *
Global Interrupt Mask/Poll Control Optional Data Flow Resume by Xon Any Character Control
Rev. 00
IN16C1054
3. Ordering Information
Table 1: Ordering Information
Part Number IN16C1054-TQ IN16C1054-PL Package 80-Pin TQFP 68-Pin PLCC Operating Temperature Range -20 to +85 -20 to +85 Device Status Active Active
4. Block Diagram
SB16C1054
D[7:0] IOR#/IOW# RESET TRANSMIT FIFO REGISTER TRANSMIT SHIFT REGISTER
DATA AND CONTROL LOGIC
TXD0
A[2:0] CS#[3:0]
REGISTER CONTROL LOGIC
FLOW CONTROL LOGIC
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXD0
FLOW CONTROL LOGIC
MODEM SIGNAL CONTROL LOGIC GLOBAL INTRRUPT CONTROL LOGIC
RTS0#/DTR0# CTS0#/DSR0#/DCD0#/RI0# TXRDY0#/RXRDY0#
INT[3:0] TXRDY#/RXRDY#
INTERRUPT CONTROL LOGIC UART 0 TXD1 RXD1 RTS1#/DTR1# CTS1#/DSR1#/DCD1#/RI1# TXRDY1#/RXRDY1# TXD2 RXD2 RTS2#/DTR2# CTS2#/DSR2#/DCD2#/RI2# TXRDY2#/RXRDY2# TXD3 RXD3 RTS3#/DTR3# CTS3#/DSR3#/DCD3#/RI3# TXRDY3#/RXRDY3# CLOCK AND BAUD RATE GENERATOR
UART 1
UART 2
UART 3
XTAL1
XTAL2
CLKSEL
Figure 1: Block Diagram
Rev. 00
IN16C1054
5. Pin Configuration
5.1 Pin Configuration for 80-Pin TQFP Package
RXRDY2#/RXEN2
CLKSEL
RESET
RXD2
GND
RXD1
A0
TXRDY2#/TXEN2 DSR2# CTS2# DTR2#/TXEN2 VCC RTS2#/TXEN2 INT2 CS2# TXD2 IOR# NC TXD3 CS3# INT3 RTS3#/TXEN3 GND DTR3#/TXEN3 CTS3# DSR3# TXRDY3#/TXEN3
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 61 62 39 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 RXRDY3#/RXEN3 2 DCD3# 3 RI3# 4 RXD3 5 VCC 6 INTSEL 7 D0 8 D1 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20 RXRDY0#/RXEN0 DCD0# NC GND RXD0 RI0# D3 D4 D5 D6 D2 D7
A1
A2
RXRDY1#/RXEN1
RXRDY#
TXRDY#
DCD2#
DCD1#
XTAL2
XTAL1
RI2#
RI1#
NC
NC
TXRDY1#/TXEN1 DSR1# CTS1# DTR1#/TXEN1 GND RTS1#/TXEN1 INT1 CS1# TXD1 IOW# NC TXD0 CS0# INT0/GINT RTS0#/TXEN0 VCC DTR0#/TXEN0 CTS0# DSR0# TXRDY0#/TXEN0
NC - No internal connection
Figure 2: 80-Pin TQFP Pin Configuration
Rev. 00
IN16C1054
5.2 Pin Configuration for 68-Pin PLCC Package
INTSEL
DCD0#
RXD0
RXD3
GND
9 DSR0# CTS0# DTR0#/TXEN0 VCC RTS0#/TXEN0 INT0/GINT CS0# TXD0 IOW# TXD1 CS1# INT1 RTS1#/TXEN1 GND DTR1#/TXEN1 CTS1# DSR1# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
VCC
DCD3#
RI0#
RI3#
D7
D6
D5
D4
D3
D2
D1
D0
DSR3# CTS3# DTR3#/TXEN3 GND RTS3#/TXEN3 INT3 CS3# TXD3 IOR# TXD2 CS2# INT2 RTS2#/TXEN2 VCC DTR2#/TXEN2 CTS2# DSR2#
26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 XTAL1 XTAL2 RXRDY# TXRDY# RXD1 DCD1# RESET CLKSEL DCD2# NC RXD2 RI1# GND RI2# A2 A1 A0
NC - No internal connection
Figure 3: 68-Pin PLCC Pin Configuration
Rev. 00
IN16C1054
5.3 Pin Description
Table 2: Pin Description Data Bus Interface
Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 IOR# Pin TQFP80 48 47 46 7 8 9 11 12 13 14 15 70 Type PLCC68 34 33 32 66 67 68 1 2 3 4 5 52 I I I I/O I/O I/O I/O I/O I/O I/O I/O I Read Data (active low strobe). A valid low level on IOR# will load the data of an internal register defined by address lines A [2:0] onto the UART data bus for access by an external CPU. Write Data (active low strobe). A valid low level on IOW# will transfer the data from external CPU to an internal register that is defined by address lines A [2:0]. Chip Select 0, 1, 2, and 3 (active low). These pins enable data transfers between the external CPU and the UART for the respective channel. Interrupt 0/Global Interrupt, Interrupt 1, 2, and 3. These pins provide individual channel interrupts or global interrupt. INT0-3 are enabled when MCR[3] is set to `1' and AFR[4] is cleared to `0' (default state). But INT0 operates as GINT and INT1-INT3 are disabled when AFR[4] is set to `1'. INT0-3's asserted state is active high, but GINT's asserted state is determined by AFR[5]. GINT's asserted state is active high when AFR[5] is set to `1', and active low when AFR[5] is cleared to `0'. Interrupt Select. When INTSEL is left open or low state, the tri-state interrupts available on INT0-3 are enabled by MCR[3]. But, when INTSEL is in high state, INT0-3 are always enabled. Description Address Bus Lines [2:0]. These 3 address lines select one of the internal registers in UART channel 0-3 during a data bus transaction. Data Bus Lines [7:0]. These pins are tri-state data bus for data transfer to or from the controlling CPU.
IOW#
31
18
I
CS0# CS1# CS2# CS3# INT0/GINT INT1 INT2 INT3
28 33 68 73 27 34 67 74
16 20 50 54 15 21 49 55
I I I I O O O O
INTSEL
6
65
I
Rev. 00
IN16C1054
Table 2: Pin Description...continued
Name TXRDY0#/TXEN0 TXRDY1#/TXEN1 TXRDY2#/TXEN2 TXRDY3#/TXEN3 Pin TQFP80 21 40 61 80 Type PLCC68 O O O O Description Transmitter Ready 0, 1, 2, and 3/Tx Enable 0, 1, 2, and 3. These pins provide individual channel transmitter ready or transmit enable. TXRDY0-3# are enabled when ATR[1:0] is cleared to `00' (default state). If ATR[1:0] are set to `11', TXRDY0-3# operate as TXEN0-3. TXRDY0-3# (active low) are asserted by TX FIFO/THR status for transmit channels 0-3. TXEN0-3's asserted state is determined by ATR[5:4]. If ATR[4] is cleared to `0', the state holds the same value as ATR[5]. If ATR[4] is set to `1', it is the auto-toggling state based on ATR[5]. If these pins are unused, leave them unconnected. Receiver Ready 0, 1, 2, and 3/Rx Enable 0, 1, 2, and 3. These pins provide individual channel receiver ready or receive enable. RXRDY0-3# are enabled when ATR[1:0] is cleared to `00' (default state). If ATR[1:0] is set to `11', RXRDY0-3# are changed to RXEN0-3. RXRDY0-3# (active low) are asserted by RX FIFO/RBR status for receive channels 0-3. RXEN0-3's asserted state is determined by ATR[7:6]. If ATR[6] is cleared to `0', the state holds the same value as ATR[7]. If ATR[6] is set to `1', it is the auto-toggling state based on ATR[7]. If these pins are unused, leave them unconnected. Transmitter Ready (active low). This is asserted by TX FIFO/THR status for transmit channels 0-3. Receiver Ready (active low). This is asserted by RX FIFO/RHR status for receive channels 0-3. Description Transmit Data. These pins are individual transmit data output. During the local loop-back mode, the TXD output pin is disabled and TXD data is internally connected to the RXD input. Receive Data. These pins are individual receive data input. During the local loop-back mode, the RXD input pin is disabled and RXD data is internally connected to the TXD output.
RXRDY0#/RXEN0 RXRDY1#/RXEN1 RXRDY2#/RXEN2 RXRDY3#/RXEN3
20 41 60 1
-
O O O O
TXRDY# RXRDY#
55 54
39 38
O O
Modem and Serial I/O Interface
Name TXD0 TXD1 TXD2 TXD3 RXD0 RXD1 RXD2 RXD3 Pin TQFP80 29 32 69 72 17 44 57 4 Type PLCC68 17 19 51 53 7 29 41 63 O O O O I I I I
Rev. 00
IN16C1054
Table 2: Pin Description...continued
Name RTS0# RTS1# RTS2# RTS3# CTS0# CTS1# CTS2# CTS3# DTR0# DTR1# DTR2# DTR3# DSR0# DSR1# DSR2# DSR3# DCD0# DCD1# DCD2# DCD3# RI0# RI1# RI2# RI3# Other Interfaces Name XTAL1 XTAL2 CLKSEL Pin TQFP80 26 35 66 75 23 38 63 78 24 37 64 75 22 39 62 79 29 32 69 72 17 44 57 4 Pin TQFP80 50 51 45 PLCC68 35 36 30 I O I Crystal or External Clock Input. Crystal or Buffered Clock Output. Clock Select. This pin selects the divide-by-1 or divide-by-4 prescalable clock. During the reset, The high on CLKSEL selects the divide-by-1 prescaler. The low on CLK selects the divide-by-4 prescaler. The inverting value of CLKSEL is latched into MCR[7] at the trailing edge of RESET. Reset (active high). This pin will reset the internal registers and all the outputs. Power Supply Input. 3.3V (2.7V ~ 3.6V) Signal and Power Ground. No Internal Connection. Type PLCC68 14 22 48 56 11 25 45 59 12 24 46 58 10 26 44 60 17 19 51 53 7 29 41 63 O O O O I I I I O O O O I I I I I I I I I I I I Type Description Request to Send (active low). These pins indicate that the UART is ready to send data to the modem, and affect transmit and receive operations only when Auto-RTS function is enabled. Clear to Send (active low). These pins indicate the modem is ready to accept transmitted data from the UART, and affect transmit and receive operations only when Auto-CTS function is enabled. Data Terminal Ready (active low). These pins indicate UART is ready to transmit or receive data.
Data Set Ready (active low). These pins indicate modem is powered-on and is ready for data exchange with UART.
Carrier Detect (active low). These pins indicate that a carrier has been detected by modem.
Ring Indicator (active low). These pins indicate the modem has received a ringing signal from telephone line. A low to high transition on these input pins generates a modem status interrupt, if enabled. Description
RESET VCC GND NC
53 5, 25, 65 16, 36, 56, 76 10, 30, 47, 52, 71
37 13, 47, 64 6, 23, 40, 57 31
I I I -
Rev. 00
IN16C1054
6. Functional Description
The IN16C1054 UART is pin-to-pin compatible with the TL16C554 and ST16C654 UARTs. IN16C1054 offers 16C450 and 16C650 modes. When FIFO is enabled, it has a register configuration compatible with 64-byte FIFO and 16C654, so it becomes compatible with 16C654. If you enable 256-byte FIFO, you use the unique supreme function that IN16C1054 offers. It offers communication speed up to 5.3Mbps and more enhanced functions that other UARTs with 128-byte FIFO do not. IN16C1054 can select hardware/software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS# output and CTS# input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters.
6.1 FIFO Operation
IN16C1054's FIFO has two modes, 64-byte FIFO mode and 256-byte FIFO mode. Setting FCR[0] to `1' enables FIFO, and if AFR[0] is set to `0', it operates in 64-byte FIFO mode(default). In this mode, Transmit Data FIFO, Receive Data and Receive Status FIFO are 64 bytes. 64-byte FIFO mode allows you to select the Transmit Interrupt Trigger Level from 8, 16, 32, or 56. You can verify this Interrupt Trigger Level by TTR and RTR. In this mode TTR and RTR are Read Only. And by FCR[5:4], XOFF Trigger Level can be selected to either 8, 16, 56, or 60, and XON Trigger Level to either 0, 8, 16, or 56 by FCR[7:6]. You can verify XON and XOFF Trigger Level by FUR and FLR. In 64-byte FIFO mode TTR and RTR are Read Only. If you select 256-byte FIFO mode, you can experience more powerful features of IN16C1054. Setting both FCR[0] and AFR[0] to `1' will enable this mode. In this mode, Transmit Data FIFO, Receive Data and Receive Status FIFO are 256 bytes. Interrupt Trigger Level and XON, XOFF Trigger Level are controlled by TTR, RTR, FUR and FLR, not by FCR[7:4]. That is, TTR, RTR, FUR and FLR can both read and write. You can verify free space of Transmit FIFO and the number of characters received in Receive FIFO by TCR, RCR and ISR[7:6]. While TX FIFO is full, the value sent to THR by CPU disappears. And while RX FIFO is full, the data coming from external devices disappear as well, provided that flow control function is not used. For more information, refer to Register Description.
6.2 Hardware Flow Control
Hardware flow control is executed by Auto-RTS and Auto-CTS. Auto-RTS and Auto-CTS can be enabled/disabled independently by programming EFR[7:6]. If Auto-RTS is enabled, it reports that it cannot receive more data by asserting RTS# when the amount of received data in RX FIFO exceeds the written value in FUR. Then after the data stored in RX FIFO is read by CPU, it reports that it can receive new data by deasseting RTS# when the amount of existing data in RX FIFO is less than the written value in FLR. When Auto-CTS is enabled and CTS# is cleared to `0', transmitting data to TX FIFO has to be suspended because external device has reported that it cannot accept more data. When data transmission has been suspended and CTS# is set to `1', data in TX FIFO is retransmitted because external device has reported that it can accept more data. These operations prevent overrun during communication and if hardware flow control is disabled and transmit data rate exceeds RX FIFO service latency, overrun error occurs.
Rev. 00
IN16C1054
6.2.1 Auto-RTS
To enable Auto-RTS, EFR[6] should be set to `1'. Once enabled, RTS# outputs `0'. If the number of received data in RX FIFO is larger than the value stored in FUR, RTS# will be changed to `1' and if not, holds `0'. This state indicates that RX FIFO can accept more data. After RTS# changed to `1' and reported to the CPU that it cannot accept more data, the CPU reads the data in RX FIFO and then the amount of data in RX FIFO reduces. When the amount of data in RX FIFO equals the value written in FLR, RTS# changes to `0' and reports that it can accept more data. That is, if RTS# is `0' now, RTS# is not changed to `1' until the amount in RX FIFO exceeds the value set in FUR. But if RTS# is `1' now, RTS# is not changed to `0' until the amount in RX FIFO equals the value written in FLR. The value of FUR and FLR is determined by FIFO mode. If FCR[7:6] holds `00', '01', `10', and `11', FUR stores 8, 16, 56, and 60, respectively. And if FCR[5:4] holds `00', '01', `10', and `11', FLR stores 0, 8, 16, and 56, respectively in 64-byte FIFO. In 256-byte FIFO mode, users can write FUR and FLR values as they want and use them. But the value of FUR must be larger than that of FLR. While Auto-RTS is enabled, you can verify if RTS# is `0' or `1' by FSR[5]. If FSR[5] is `0', RTS# is `0' and if `1', RTS# is `1', too. When IER[6] is set to `1' and RTS# is changed from `0' to `1' by Auto-RTS function, interrupt occurs and it is displayed on ISR[5:0]. Interrupts by Auto-RTS function are removed if MSR is read. RTS# is changed from `0' to `1' after the first STOP bit is received. Figure 4 shows the RTS# timing chart while Auto-RTS is enabled. In Figure 4, Data Byte n-1 is received and RTS# is deasserted when the amount of data in RX FIFO is larger than the value written in FUR. UART completes transmitting new data (DATA BYTE n) which has started being transmitted even though external UART recognizes RTS# has been deasserted. After that, the device stops transmitting more data. If CPU reads data of RX FIFO, the value of RCR decreases and then if that value equals that of FLR, RTS# is asserted for external UART to transmit new data.
RXD
START
DATA BYTE n-1
STOP
START
DATA BYTE n
STOP
START
RTS#
DATA BYTE 1 DATA BYTE 2 DATA BYTE n
IOR#
RCR[7:0]
FUR + 0
FUR + 1
FUR -0
FUR - 1
FUR - 0
FLR + 1
FLR + 0
Figure 4: RTS# Functional Timing
Rev. 00
IN16C1054
6.2.2 Auto-CTS
Setting EFR[7] to `1' enables Auto-RTS. If enabled, data in TX FIFO are determined to be transmitted or suspended by the value of CTS#. If `0', it means external UART can receive new data and data in TX FIFO are transmitted through TXD pin. If `1', it means external UART can not accept more data and data in TX FIFO are not transmitted. But data being transmitted by then complete transmission. These procedures are performed irrespective of FIFO modes. While Auto-CTS is enabled, you can verify the input value of CTS# by FSR[1]. If `0', CTS# is `0' and it means external UART can accept new data, If '1', CTS# is `1' and it means external UART can not accept more data and data in TX FIFO are not being transmitted. If IER[7] is set to `1', interrupt is generated by Auto-CTS when the input of CTS# is changed from `0' to `1', and it is shown on ISR[5:0]. Interrupts generated by Auto-CTS are removed if MSR is read.
Rev. 00
IN16C1054
6.3 Software Flow Control
Software flow control is performed by Xon and Xoff character transmitting/accepting. Software flow control is enabled/disabled independently by programming EFR[3:0] and MCR[6:5, 2]. If TX software flow control is enabled by EFR[3:2], Xoff character is transmitted to report that data can not be accepted when the stored amount of data in RX FIFO exceeds the value in FUR. After the CPU reads the data in RX FIFO and if the read amount is less than the value in FLR, Xon character is transmitted to report that more data can be accepted. If TX software flow control is enabled by EFR[1:0] and Xoff character is inputted through RXD pin, it means no more data can be accepted, and data transmission is suspended even though data are in TX FIFO. If Xon character is received through RXD pin while data transmission is suspended, it means more data can be accepted, and therefore data in TX FIFO are re-transmitted. These procedures prevent overruns during communication. If software flow control is disabled, overrun occurs when the transmit data rate exceeds RX FIFO service latency. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0] . Table 3 shows software flow control options.
Table 3: Software flow control options (EFR[3:0])
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow controls 0 1 0 1 X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 No transmit control Transmit Xon1/Xoff1 Transmit Xon2/Xoff2 Transmit Xon1, Xon2/Xoff1, Xoff2 No receive flow control Receiver compares Xon1/Xoff1 Receiver compares Xon2/Xoff2 Receiver compares Xon1, Xon2/Xoff1, Xoff2 No transmit control, No receive flow control No transmit control, Receiver compares Xon1/Xoff1 No transmit control, Receiver compares Xon2/Xoff2 No transmit control, Receiver compares Xon1, Xon2/Xoff1, Xoff2 Transmit Xon1/Xoff1, No receive flow control Transmit Xon1/Xoff1, Receiver compares Xon1/Xoff1 Transmit Xon1/Xoff1, Receiver compares Xon2/Xoff2 Transmit Xon1/Xoff1, Receiver compares Xon1, Xon2/Xoff1, Xoff2 Transmit Xon2/Xoff2, No receive flow control Transmit Xon2/Xoff2, Receiver compares Xon1/Xoff1 Transmit Xon2/Xoff2, Receiver compares Xon2/Xoff2 Transmit Xon2/Xoff2, Receiver compares Xon1, Xon2/Xoff1, Xoff2 Transmit Xon2/Xoff2, No receive flow control Transmit Xon2/Xoff2, Xoff2, Receiver compares Xon1/Xoff1 Transmit Xon1, Xon2/Xoff1, Xoff2, Receiver compares Xon2/Xoff2 Transmit Xon1, Xon2/Xoff1, Xoff2, Receiver compares Xon1, Xon2/Xoff1, Xoff2
Rev. 00
IN16C1054
6.3.1 Transmit Software Flow Control
To make Transmit Software Flow Control enabled, EFR[3:2] must be set to `01', `10' or `11'. Unlike Auto-RTS in which `0' is outputted on RTS# when TX software flow control function is enabled, Xon character is not transmitted at first. If the amount of data in RX FIFO (written in ISR[6] and RCR) is less than the value in FUR, Xon character is not transmitted because Xon is in initial state. But if the amount of data in RX FIFO exceeds the value in FUR, Xoff character is transmitted immediately. Transmitting Xoff character means no more data can be accepted and after CPU reads data in RX FIFO, data in RX FIFO decreases. When the amount of data in RX FIFO is same as the value of FLR, Xon character is transmitted and it means reporting to external UART that it can accept more data. After transmitting Xoff character, Xon character is not transmitted until the amount of data in RX FIFO is same as the value of FLR. The value of FLR is determined by FIFO mode. If FCR[7:6] is `00', '01', `10', and `11', FUR is 8, 16, 56, and 60, respectively. And if FCR[5:4] is `00', '01', `10', and `11', FLR is 0, 8, 16, and 56, respectively in 64-byte FIFO. In 256-byte FIFO mode, users can input values in FUR and FLR as they want and use them. But the value in FUR must be larger than that of FLR. While TX software flow control is active, its status (if Xon or Xoff) can be verified by FSR[4]. If FSR[4] is `0', the status is Xon and if `1', the status is Xoff. It can be verified by FSR[4] only. And for there is no condition to generate interrupt, interrupt doesn't occur. It is different from that interrupt is generated by IER[5] when RX software flow control is enabled.
6.3.2 Receive Software Flow Control
To make Receive Software Flow Control enabled, EFR[1:0] must be set to `01', `10' or `11'. When enabled, data in TX FIFO are determined to be transmitted or suspended by incoming Xon/Xoff characters. If Xon character is received, it means external UART can accept new data, and data in TX FIFO are transmitted through TXD pin. If Xoff character is received, it means external UART can not accept more data, and data in TX FIFO are not transmitted. But data being transmitted by that time are completely transmitted. These procedures are performed irrespective of FIFO modes. While Receive Software Flow Control is enabled, you can verify if the RX Software Flow Control status is XON or XOFF by FSR[0]. If it is `0', RX Software Flow Control status is XON and it means external UART can accept new data. If '1', RX Software Flow Control status is XOFF and it means external UART can not accept more data and data in TX FIFO are not being transmitted. If IER[5] is set to `1', interrupt is generated when Xoff character is received and it is shown on ISR[5:0]. Interrupts generated by RX Software Flow Control are removed if ISR is read or Xon character is received. General problems in using XON/XOFF function and tips for using Xon/Xoff character as one character are as follows. When RX Software Flow Control and Auto-CTS are enabled, LSR's Transmit Empty Bit and Transmit Holding Empty Bit are not affected even though RX Flow Control status is XOFF or `1' is inputted on CTS# pin, so data in TX FIFO are suspended. That is, these two bits are set to `1' if there is space available in TX FIFO. Xon/Xoff character which generated parity error are treated as normal Xon/Xoff character. If Xon and Xoff character are set to same, both characters are treated as Xon character.
Tips for using Xon/Xoff character as two characters are as follows.
Rev. 00
IN16C1054
If received characters are Xon1, Xon1 and Xon2, RX flow control status becomes XON and previous Xon1 is ignored. If received characters are Xoff1, Xoff1 and Xoff2, RX flow control status becomes XOFF and previous Xoff1 is ignored. If received characters are repeated as Xon1 Xoff1, Xon1 and Xoff1, there is no effect in RX flow control status and these characters are not treated as data. But if received characters are Xon1 Xoff1, Xon1, Xoff1, Xon1 and Xon2, RX flow control status becomes XON. If received characters are Xon1 Xoff1, Xon1, Xoff1 and Xoff2, RX flow control status becomes XOFF. If Xon1 and Xoff1 characters do not precede Xon2 and Xoff2, Xon2 and Xoff2 are treated as data and stored in RX FIFO. If Xon1 is not accompanied with Xon2 or Xoff1 character, it is treated as data and stored in RX FIFO. If Xoff1 is not accompanied with Xoff2 or Xon1 character, it is treated as data and stored in RX FIFO. As seen before, if received characters are Xon1, Xoff2, Xon2 or Xoff1, Xon2, Xoff2, these characters are all treated as data and stored in RX FIFO. If characters are arrived continuously like Xon1, Xon2 or Xoff1, Xoff2, descriptions are as follows. If Xon1, Xon2 characters and Xoff1, Xoff2 characters are same with each other, all characters are treated as normal XON and XOFF characters. If Xon1, Xoff1 characters and Xon2, Xoff2 characters are same with each other, these are treated as normal XON characters. If Xon1, Xon2, Xoff1 characters are same and Xoff2 is different, these are treated as normal XON, XOFF characters. If Xon1, Xon2, Xoff2 characters are same and Xoff1 is different, these are treated as normal XON, XOFF characters. If Xon2, Xoff1, Xoff2 characters are same and Xon1 is different, these are treated as normal XON, XOFF characters. If Xon1, Xoff1, Xoff2 characters are same and Xon2 is different, these are treated as normal XON, XOFF characters. If Xon2, Xoff1 characters are same and Xon1, Xoff2 are different, these are treated as normal XON, XOFF characters. If Xon1, Xon2, Xoff1, Xoff2 are all same, these are treated only as normal XON characters. In all these cases no XON/XOFF characters are treated as data. Refer to Table 4 below.
Table 4: Xon/Xoff Character Recognition Logic Table
Rev. 00
IN16C1054
Xon1 Char. 11h 11h 11h 11h 11h 11h 11h 11h
Xon2 Char. 11h 13h 11h 11h 13h 13h 13h 11h
Xoff1 Char. 13h 11h 11h 13h 13h 11h 13h 11h
Xoff2 Char. 13h 13h 13h 11h 13h 11h 14h 11h
Recognition of Xon Char. Yes Yes Yes Yes Yes Yes Yes Yes
Recognition of Xoff Char. Yes No Yes Yes Yes Yes Yes No
In case XON/XOFF software flow control function and Xon Any function is enabled, descriptions are as follows. If Xon, Xoff characters are used as one character, If Xoff character arrives during XON status, status changes to XOFF. If Xon character arrives during XOFF status, status changes to XON. If Xoff character arrives during XOFF status, status changes to XON but Xoff character is not treated as data. If Xon, Xoff characters are used as two characters, If only Xon1 or Xon1 + Xon2 character arrives during Xoff status, status changes to Xon and all characters are not treated as data. If only Xon2 character arrives during Xoff status, status changes to Xon and Xon2 character is treated as data and stored in RX FIFO. If Xoff1 + Xoff2 character arrives during XON status, status changes to XON. If Xoff1 + Xoff2 character arrives during XOFF status, status is changed to XON by Xoff1 and changed to XOFF again by Xoff2. In case Software flow control function and Special character function is enabled, descriptions are as follows. If Xoff1 character is used as Software flow control character, character in Xoff2 Register is recognized as Special character. If Xoff2 character is used as Software flow control character, it is not recognized as Special character but as Xoff character because both are same. If Xoff1, Xoff2 character is sequential and Xoff1 + Xoff2 character is used as Software flow control character, it is not recognized as Special character but as Xoff2 character because both are same. If Xoff1 + Xoff2 character is used as Software flow control character and Xoff2 character which does not follow after Xoff1 character arrives, it is not recognized as Xoff2 character but as Special character even though both are same.
Rev. 00
IN16C1054
6.3.3 Xon Any Function
While RX Software flow control function is enabled, data in TX FIFO are transmitted when received Xon character and transmission is suspended when Xoff character is received. This status is called `XOFF status'. Transmission is re-started when status changes to `XON status' by incoming Xon character or Xon Any function that changes status when any data arrives. Xon Any function is enabled if MCR[5] is set to `1'. While it is enabled, XOFF status changes to XON status though Xoff character arrives. Details about it are described in 6.3.2 Receive Software Flow Control.
6.3.4 Xoff Re-transmit Function
While TX Software flow control function is active, Xoff character is transmitted when the amount of data in RX FIFO exceeds the value of FUR. Though it received Xoff character, external UART may not recognize this character for some reason and continue to transmit data. Under TX Software flow control, because Xoff character had been transmitted once before, it is not transmitted again though more data arrive. In this situation, overflow may occur in RX FIFO. Conventional UARTs can not deal this situation but SB16C1054 does with Xoff Re-transmit function. Xoff Re-transmit function transmits Xoff character again when more data arrives from external UART though it transmitted Xoff character before. By this function the external UART can recognize Xoff character and stop transmitting data though it didn't recognize the Xoff character before. There are four Xoff Re-transmitting settings by XRCR[1:0]. Xoff character can be retransmitted when every 1, 4, 8 or 16 data arrives in XOFF status. If XRCR[1:0] is `00', Xoff character is re-transmitted whenever 1 more data arrives in XOFF status. If XRCR[1:0] is `01', Xoff character is re-transmitted whenever 4 more data arrives in XOFF status. If `10', 8 more data and if `11', 16 more data. If the value of FUR is approaching the FIFO size, 256-byte, it is good to write XRCR[1:0] `00'. If the 256-FUR value is small, it is good to select `00' of XRCR and if large, it is good to select `11'. Xoff Re-transmit function is enabled by MCR[6] and MCR[2]. Change MCR[2] from OP1# function to Xoff Re-transmit function by setting MCR[6] to `1' and set MCR[2] to `1' again. Then Xoff Re-transmit function is enabled. When disabling it, first set MCR[6] to `1' and then clear MCR[2] to `0'.
Rev. 00
IN16C1054
6.4 Interrupts
As there are four independent 1-channel UARTs in SB16C1054, so there are four interrupts. Interrupts are assigned INT0, INT1, INT2, and INT3 for each channel. Each interrupt has six prioritized level's interrupt generation capability. The IER enables each of the six types of interrupts and INT signal in response to an interrupt generation. When an interrupt is generated, the ISR indicates that an interrupt is pending and provides the type of interrupt. And SB16C1054 can handle for four interrupts with one global interrupt. Global interrupt treats four of each interrupt as one interrupt, so it is useful when external system has few interrupt resource. Global interrupt line is also used as INT0, and it is determined by AFR[4] that which one is used. If AFR[4] is cleared to `0', INT0/GINT pin is selected as INT0 and if set to `1', GINT. When you treat four interrupts as one interrupt, you should use several additional functions. GICR determines whether global interrupt occurs or not. While GICR[0] is set to `1', an interrupt that is generated in four onechannel UARTs and treated as UNMASK is transmitted to GINT. But if GICR[0] is cleared to `0', an interrupt is not transmitted to GINT though interrupts are generated in four onechannel UARTs and treated as MASK. So this interrupt is not transmitted to external CPU. The status of global interrupt and generation of interrupts in one-channel UART can be verified by GISR. The value set in GICR[0] is reflected in GISR[7], so the status of mask of global interrupt can be verified. GISR[0] shows the status of interrupt of UART that is connected to CS0#. If GISR[0] is cleared to `0', it means that interrupt is not generated in the UART of CS0# and if set to `1', it means that interrupt is generated. The value of GISR[0] shows the status of interrupt generated in the UART of CS0#, irrespective of the value set in GICR[0]. GICR[0] determines whether the interrupts generated in four one-channel UARTs that is connected to CS0#, CS1#, CS2#, and CS3# are transmitted to external devices or not, but does not determine whether the interrupts are generated or not in UARTs. The value of output signal when an interrupt is generated in GINT pin is selected by AFR[5]. That is, GINT can determine the polarity of asserted status. If AFR[5] is cleared to `0', GINT outputs `0' when global interrupt is generated. And if set to `1', outputs `1' when global interrupt is generated.
Rev. 00
IN16C1054
6.5 DMA Operation
Transmitter and Receiver DMA operation is available through TXRDY#, RXRDY#, TXRDY[3:0]#, and RXRDY[3:0]#. There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[3] = 0), DMA occurs in single character transfer. In DMA mode 1, multi-character DMA transfers are managed to relieve the CPU for longer periods of time.
6.5.1 Single DMA transfer (DMA Mode 0/FIFO Disable)
Transmitter: There are no character in TX FIFO or THR. And the TXRDY# and TXRDY[3:0]# signals will be in assert state. TXRDY#, TXRDY[3:0]# will switch to deassert state after one character is loaded into TX FIFO or THR. Receiver: There is at least one character in RX FIFO or RHR. And the RXRDY# and RXRDY[3:0]# signals will be in assert state. Once RXRDY# is asserted, RXRDY[3:0]# signal will switch to deassert state when there are no more characters in RX FIFO or RBR. Figure 5 shows TXRDY#, TXRDY[3:0]#, RXRDY#, and RXRDY[3:0]# in DMA mode 0/FIFO disable.
TX FIFO
RX FIFO
EMPTY SPACE
TXRDY#, TXRDY[3:0]#
EMPTY SPACE
RXRDY#, RXRDY[3:0]#
ISR[7]
0
TCR
01h Character #1
AT LEAST ONE LOCATION FILLED
ISR[6]
0
RCR
01h Character #1
AT LEAST ONE LOCATION FILLED
TXRDY#, TXRDY[3:0]#
RXRDY#, RXRDY[3:0]#
ISR[7]
1
TCR
00h TX FIFO EMPTY
ISR[6]
0
RCR
00h RX FIFO EMPTY
Figure 5: TXRDY#/TXRDY[3:0]# and RXRDY#/RXRDY[3:0]# in DMA mode 0/FIFO disable.
Rev. 00
IN16C1054
6.5.2 Block DMA transfer (DMA Mode 1)
Transmitter: When the characters in TX FIFO are less than the trigger level that is set in TTR, TXRDY# or TXRDY[3:0] signal is asserted. When TX FIFO is full, TXRDY# or TXRDY[3:0]# signal is deasserted. Receiver: When the characters in RX FIFO are more than the trigger level that is set in RTR, RXRDY# or RXRDY[3:0] signal is asserted. When RX FIFO is empty, RXRDY# or RXRDY[3:0]# signal is deasserted. The figure 6 below shows TXRDY#, TXRDY[3:0]# and RXRDY#, RXRDY[3:0]# in DMA mode 1.
TX FIFO
Character #256 Character #255
RX FIFO
EMPTY SPACE
TTR
80h Character #128 Character #127
TXRDY#, TXRDY[3:0]#
RTR
80h Character #128 Character #127
RXRDY#, RXRDY[3:0]#
ISR[7]
0
TCR
00h
Character #2 Character #1
TX FIFO FULL
ISR[6]
0
RCR
80h
Character #2 Character #1
EMPTY SPACE
TTR
80h Character #128 Character #127
TXRDY#, TXRDY[3:0]#
RTR
80h
RXRDY#, RXRDY[3:0]#
ISR[7]
0
TCR
80h
Character #2 Character #1
ISR[6]
0
RCR
00h RX FIFO EMPTY
Figure 6: TXRDY#/TXRDY[3:0]# and RXRDY#/RXRDY[3:0]# in DMA mode 1.
6.6 Sleep Mode with Auto Wake-Up
The SB16C1054 provides sleep mode operation to reduce its power consumption when sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to `1'. Sleep mode is activated when: RXD input is in idle state. CTS#, DSR#, DCD#, and RI# are not toggling. The TX FIFO and TSR are in empty state. No interrupt is pending except THR and time-out interrupts.
In sleep mode, the SB16C1054 clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. Normal operation is resumed when: RXD input receives the data start bit transition. Data byte is loaded to the TX FIFO or THR. CTS#, DSR#, DCD#, and RI# inputs are changed.
Rev. 00
IN16C1054
6.7 Programmable Baud Rate Generator
The SB16C1054 has a programmable baud rate generator with a prescaler. The prescaler is controlled by MCR[7], as shown in Figure 7. The MCR[7] sets the prescaler to divide the clock frequency by 1 or 4. And the baud rate generator further divides this clock frequency by a programmable divisor (DLL and DLM) between 1 and (216 - 1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by transmitter for data bit shifting and receiver for data sampling. The divisor of the baud rate generator is: ( XTAL1 Crystal Input Frequency Divisor = Prescaler (Desired Baud Rate x 16)
)
MCR[7] is cleared to `0' (prescaler = 1), when CLKSEL input is in low state after reset. MCR[7] is set to `1' (prescaler = 4), when CLKSEL input is in high state after reset.
PROGAMMABLE DIVISOR PRESCALER LOGIC (DIVIDE BY 1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC PRESCALER LOGIC (DIVIDE BY 4) MCR[7] = 0 INTERNAL BAUD RATE CLOCK FOR TRANSMITTER AND RECEIVER
REFERENCE CLOCK MCR[7] = 1
BAUD RATE GENERATOR LOGIC
Figure 7: Prescaler and Baud Rate Generator Block Diagram
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are both zero, the SB16C1054 is effectively disabled, as no baud clock will be generated. Table 5 shows the baud rate and divisor value for prescaler with divide by 1 as well as crystal with frequency 1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.7456MHz, respectively. Figure 8 shows the crystal clock circuit reference.
Table 5: Baud Rates
Rev. 00
IN16C1054
Desired Baud Rate 1.8432MHz 50 75 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19.2K 38.4K 57.6K 115.2K 230.4K 460.8K 921.6K 0900h 0600h 0300h 0180h 00C0h 0060h 0040h 003Ah 0030h 0020h 0018h 0010h 000Ch 0006h 0003h 0002h 0001h
16X Digit Divisor for Prescaler with Divide by 1 3.6864MHz 1200h 0C00h 0600h 0300h 0180h 00C0h 0080h 0074h 0060h 0040h 0030h 0020h 0018h 000Ch 0006h 0004h 0002h 0001h 7.3728MHz 2400h 1800h 0C00h 0600h 0300h 0180h 0100h 00E8h 00C0h 0080h 0060h 0040h 0030h 0018h 000Ch 0008h 0004h 0002h 0001h 14.7456MHz 4800h 3000h 1800h 0C00h 0600h 0300h 0200h 01D0h 0180h 0100h 00C0h 0080h 0060h 0030h 0018h 0010h 0008h 0004h 0002h 0001h
External Clock
XTAL1 XTAL1 R1 CRYSTAL R2
SB16C1054
XTAL2
SB16C1054
Optional Clock Output XTAL2 C1 C2
Figure 8: Prescaler and Baud Rate Generator Block Diagram Table 6: Component Values
Frequency Range (MHz) 1.8~8 8~16 C1 (pF) 22 33~68 C2 (pF) 68 33 ~ 68 R1 () 220K 220K ~ 2.2M R2() 470 ~ 1.5K 470 ~ 1.5K
6.8 Break and Time-out Conditions
Rev. 00
IN16C1054
Break Condition: Break Condition is occurred when TXD signal outputs `0' and sustains for more than one character. It is occurred if LCR[6] is set to `1' and deleted if `0'. If break condition is occurred when normal data are transmitted on TXD, break signal is transmitted and internal serial data are also transmitted, but they are not outputted to external TXD pin. When Break condition is deleted, then they are transmitted to TXD pin. Figure 9 below shows the Break Condition Block Diagram. Time-out Condition: When serial data is received from external UART, characters are stored in RX FIFO. When the number of characters in RX FIFO reaches the trigger level, interrupt is generated for the CPU to treat characters in RX FIFO. But when the number of characters in RX FIFO does not reach the trigger level and no more data arrives from external device, interrupt is not generated and therefore CPU cannot recognize it. SB16C1054 offers time-out function for this situation. Time-out function generates an interrupt and reports to CPU when the number of RX FIFO is less than trigger level and no more data receives for four character time. Time-out interrupt is enabled when IER[2] is set to `1' and can be verified by ISR.
TX FIFO
TSR Output
M S R L S R M S R L S R
Character #2 Character #1 MCR[6] = 0 MCR[6] = 1 MCR[6] = 0
16X Clock
Transmitter Shift Register(TSR) MCR[6] = 0
M S R
Brake Condition Output
L S R
TXD PIN MCR[6] = 1
Figure 9: Break Condition Block Diagram
Rev. 00
IN16C1054
7. Register Descriptions
Each UART channel in the SB16C1054 has its own set of registers selected by address lines A2, A1, and A0 with a specific channel selected. The complete register set is shown on Table 7 and Table 8.
Table 7: Internal Registers Map
Address A[2:0] 0h 1h 2h 3h 4h 5h 6h 7h Page 0 LCR[7] = 0 MCR[6] = 0 THR/RBR IER Page 1 LCR[7] = 1 LCR[7:0] BFh DLL DLM FCR/ISR MCR LSR MSR SPR TCR RCR FSR Page 2 LCR[7] = 0 MCR[6] = 1 -- GICR GISR LCR Page 3 LCR = BFh PSR[0] = 0 PSR ATR EFR XON1 XON2 XOFF1 XOFF2 Page 4 LCR = BFh PSR[0] = 1 PSR AFR XRCR TTR RTR FUR FLR
Rev. 00
IN16C1054
Table 7: Internal Registers Map...continued
Address A[2:0] Page 0 Registers 0h 1h 2h 3h 4h THR : Transmit Holding Register RBR : Receive Buffer Register IER : Interrupt Enable Register FCR : FIFO Control Register ISR : Interrupt Status Register LCR : Line Control Register MCR : Modem Control Register Write-only Read-only Read/Write Write-only Read-only Read/Write Read/Write LCR[7] = 0, MCR[6] = 0 LCR[7] = 0, MCR[6] = 0 LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh -- LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh, LCR[7] = 0, MCR[6] = 1 5h 6h 7h LSR : Line Status Register MSR : Modem Status Register SPR : Scratch Pad Register Page 1 Registers 0h 1h 2h 3h 4h DLL : Divisor Latch LSB DLM : Divisor Latch MSB FCR : FIFO Control Register ISR : Interrupt Status Register LCR : Line Control Register MCR : Modem Control Register Read/Write Read/Write Write-only Read-only Read/Write Read/Write LCR[7] = 1, LCR BFh LCR[7] = 1, LCR BFh LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh -- LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh, LCR[7] = 0, MCR[6] = 1 5h 6h 7h LSR : Line Status Register MSR : Modem Status Register SPR : Scratch Pad Register Read-only Read-only Read/Write LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh Read-only Read-only Read/Write LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh Register Read/Write Comments
Rev. 00
IN16C1054
Table 7: Internal Registers Map...continued
Address A[2:0] 0h 1h 2h 3h 4h Page 2 Registers None GICR : Global Interrupt Control Register GISR : Global Interrupt Status Register LCR : Line Control Register MCR : Modem Control Register -- Write-only Read-only Read/Write Read/Write -- LCR[7] = 0, MCR[6] = 1 LCR[7] = 0, MCR[6] = 1 -- LCR[7] = 0, MCR[6] = 0, LCR[7] = 1, LCR BFh, 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h TCR : Transmit FIFO Count Register RCR : Receive FIFO Count Register FSR : Flow Control Status Register Page 3 Registers PSR : Page Select Register ATR : Auto Toggle Control Register EFR : Enhanced Feature Register LCR : Line Control Register XON1 : Xon1 Character Register XON2 : Xon2 Character Register XOFF1 : Xoff1 Character Register XOFF2 : Xoff2 Character Register Page 4 Registers PSR : Page Select Register AFR : Additional Feature Register XRCR : Xoff Re-transmit Count Register LCR : Line Control Register TTR : Transmit FIFO Trigger Level Register RTR : Receive FIFO Trigger Level Register FUR : Flow Control Upper Threshold Register FLR : Flow Control Lower Threshold Register Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write LCR = BFh, PSR[0] = 0, LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 1 -- LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 1 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write LCR = BFh, PSR[0] = 0, LCR = BFh, PSR[0] = 1 LCR = BFh, PSR[0] = 0 LCR = BFh, PSR[0] = 0 -- LCR = BFh, PSR[0] = 0 LCR = BFh, PSR[0] = 0 LCR = BFh, PSR[0] = 0 LCR = BFh, PSR[0] = 0 Read-only Read-only Read-only LCR[7] = 0, MCR[6] = 1 LCR[7] = 0, MCR[6] = 1 LCR[7] = 0, MCR[6] = 1 LCR[7] = 0, MCR[6] = 1 Register Read/Write Comments
Rev. 00
IN16C1054
Table 8: Internal Registers Description
Addr. A[2:0] 0h 0h 1h Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page 0 Registers THR RBR IER Bit 7 Bit 7 0/CTS# Interrupt Enable Bit 6 Bit 6 0/RTS# Interrupt Enable Bit 5 Bit 5 0/Xoff Interrupt Enable Bit 4 Bit 4 0/Sleep Mode Enable Bit 3 Bit 3 Modem Status Interrupt Enable Interrupt Priority Bit 3 DMA Mode Select Parity Enable OUT2/ INTx Enable Bit 2 Bit 2 Receive Line Status Interrupt Enable Interrupt Priority Bit 2 TX FIFO Reset Bit 1 Bit 1 THR Empty Interrupt Enable Interrupt Priority Bit 1 RX FIFO Reset Bit 0 Bit 0 Receive Data Available Interrupt Enable Interrupt Priority Bit 0 FIFO Enable
2h
ISR
2h
FCR
3h
LCR
FCR[0]/ 256-TX FIFO Empty RX Trigger Level (MSB) Divisor Enable Clock Select
FCR[0]/ 256-RX FIFO Full RX Trigger Level (LSB) Set TX Brake Page 2 Select/Xoff Re-Transmit Access Enable THR & TSR Empty RI# Bit 6 Bit 6 Bit 14 0
Interrupt Priority Bit 5 0/TX Trigger Level (MSB) Set Parity 0/Xon Any
Interrupt Priority Bit 4 0/TX Trigger Level (LSB) Parity Type Select 0/Loop Back
Stop Bits OUT1/ Xoff ReTransmit Enable Parity Error
4h
MCR
Word Length Bit 1 RTS#
Word Length Bit 0 DTR#
5h
LSR
6h 7h 0h 1h 1h
MSR SCR DLL DLM GICR
RX FIFO Data Error DCD# Bit 7 Bit 7 Bit 15 0
THR Empty DSR# Bit 5 Bit 5 Bit 13 0
Receive Break CTS# Bit 4 Bit 4 Bit 12 0
Framing Error
Overrun Error
Receive Data Ready
DCD#
Bit 3 Bit 3 Bit 11 0
RI#
Bit 2 Bit 2 Bit 10 0
DSR#
Bit 1 Bit 1 Bit 9 0
CTS#
Bit 0 Bit 0 Bit 8 Global Interrupt Mask CH 0 Interrupt Status Bit 0 Bit 0 RX SW Flow Control Status
Page 1 Registers
Page 2 Registers
2h
GISR
5h 6h 7h
TCR RCR FSR
Global Interrupt Mask Status Bit 7 Bit 7 0
0
0
0
CH 3 Interrupt Status Bit 3 Bit 3 0
CH 2 Interrupt Status Bit 2 Bit 2 0
CH 1 Interrupt Status Bit 1 Bit 1 RX HW Flow Control Status
Bit 6 Bit 6 0
Bit 5 Bit 5 TX HW Flow Control Status
Bit 4 Bit 4 TX SW Flow Control Status
Table 8: Internal Registers Description...continued
Rev. 00
IN16C1054
Addr. A[2:0] 0h 1h Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page 3 Registers PSR ATR 1 RXEN Polarity Select Auto-CTS# Enable 0 RXEN Enable 1 TXEN Polarity Select Special Character Detect Enable Bit 5 Bit 5 Bit 5 Bit 5 Global Interrupt Polarity Select 0 Bit 5 Bit 5 Bit 5 Bit 5 0 TXEN Enable 0 0 1 0 0 Auto Toggle Mode Bit 1 Software Flow Control Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 Page Select Auto Toggle Mode Bit 0 Software Flow Control Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 256-FIFO Enable
2h
EFR
Auto-RTS# Enable
Enhanced Feature Enable Bit 4 Bit 4 Bit 4 Bit 4 Global Interrupt Enable 0 Bit 4 Bit 4 Bit 4 Bit 4
4h 5h 6h 7h 1h
XON1 XON2 XOFF1 XOFF2 AFR
Bit 7 Bit 7 Bit 7 Bit 7 0
Bit 6 Bit 6 Bit 6 Bit 6 0
Software Flow Control Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Software Flow Control Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 0
Page 4 Registers
0
2h 4h 5h 6h 7h
XRCR TTR RTR FUR FLR
0 Bit 7 Bit 7 Bit 7 Bit 7
0 Bit 6 Bit 6 Bit 6 Bit 6
0 Bit 3 Bit 3 Bit 3 Bit 3
0 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
7.1 Transmit Holding Register (THR, Page 0)
The transmitter section consists of the Transmit Holding Register (THR) and Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO or a 256-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location zero of the FIFO is used to store the byte. Characters are lost if overflow occurs.
7.2 Receive Buffer Register (RBR, Page 0)
The receiver section consists of the Receive Buffer Register (RBR) and Receive Shift Register (RSR). The RBR is actually a 64-byte FIFO or a 256-byte FIFO. The RSR receives serial data from external terminal. The serial data is converted to parallel data and is transferred to the RBR. This receiver section is controlled by the line control register. If the FIFO is disabled, location zero of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RBR also stores the error status bits associated with each character.
7.3 Interrupt Enable Register (IER, Page 0)
IER enables each of the seven types of Interrupt, namely receive data ready, transmit
Rev. 00
IN16C1054
empty, line status, modem status, Xoff received, RTS# state transition from low to high, and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are cleared. Interrupt is enabled by setting appropriate bits. Table 9 shows IER bit settings.
Table 9: Interrupt Enable Register Description
Bit 7 Symbol IER[7] Description CTS# Interrupt Enable (Requires EFR[4] = 1). 0 : Disable the CTS# interrupt (default). 1 : Enable the CTS# interrupt. 6 IER[6] RTS# Interrupt Enable (Requires EFR[4] = 1). 0 : Disable the RTS# interrupt (default). 1 : Enable the RTS# interrupt. 5 IER[5] Xoff Interrupt Enable (Requires EFR[4] = 1). 0 : Disable the Xoff interrupt (default). 1 : Enable the Xoff interrupt. 4 IER[4] Sleep Mode Enable (Requires EFR[4] = 1). 0 : Disable sleep mode (default). 1 : Enable sleep mode. 3 IER[3] Modem Status Interrupt Enable 0 : Disable the modem status register interrupt (default). 1: Enable the modem status register interrupt. 2 IER[2] Receive Line Status Interrupt Enable 0 : Disable the receive line status interrupt (default). 1: Enable the receive line status interrupt. 1 IER[1] Transmit Holding Register Interrupt Enable 0 : Disable the THR interrupt (default). 1 : Enable the THR interrupt. 0 IER[0] Receive Buffer Register Interrupt Enable 0 : Disable the RBR interrupt (default). 1 : Enable the RBR interrupt.
7.4 Interrupt Status Register (ISR, Page 0)
The UART provides multiple levels of prioritized interrupts to minimize software work load. ISR provides the source of interrupt in a prioritized manner.
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Table 10 shows ISR[7:0] bit settings.
Table 10: Interrupt Status Register Description
Bit 7 Symbol ISR[7] Description FCR[0]/256 TX FIFO Empty. When 256-byte FIFO mode is disabled (default). Mirror the content of FCR[0]. When 256-byte FIFO mode is enabled. 0 : 256-byte TX FIFO is full. 1 : 256-byte TX FIFO is not full. When TCR is `00h', there are two situations of TX FIFO full and TX FIFO empty. If 256 TX empty bit is `1', it means TX FIFO is empty and if `0', it means 256 bytes character is fully stored in TX FIFO. 6 ISR[6] FCR[0]/256 RX FIFO Full. When 256-byte FIFO mode is disabled (default). Mirror the content of FCR[0]. When 256-byte FIFO mode is enabled. 0 : 256-byte RX FIFO is not full. 1 : 256-byte RX FIFO is full. When RCR is `00h', there are two situations of RX FIFO full and RX FIFO empty. If 256 RX empty bit is `1', it means 256 bytes character is fully stored in RX FIFO and if `0', it means RX FIFO is empty.
Table 10: Interrupt Status Register Description...continued
Bit 5:0 00_0001 00_0110 00_1100 00_0100 Interrupt Priority List and Reset Functions Priority 1 2 2 Interrupt Type None Receiver Line Status Receive Data Available Character Timeout Indication 00_0010 3 Transmit Holding Register Empty 00_0000 01_0000 10_0000 4 5 6 Modem Status Receive Xoff or Special Character RTS#, CTS# Status during Auto RTS/CTS flow control Interrupt Source None OE, PE, FE, BI Receiver data available, reaches trigger level. At least one data is in RX FIFO and there are no more data in FIFO during four character time. When THR is empty or TX FIFO passes above trigger level (FIFO enable). CTS#, DSR#, DCD#, RI# Detection character. RTS# pin or CTS# pin change state from `0' to `1'. Reading the ISR. of a Xoff or special Reading the MSR. Reading the ISR. Reading the ISR or write data on THR. Interrupt Reset Control Reading the LSR. Reading the RBR or FIFO falls below trigger level. Reading the RBR.
7.5 FIFO Control Register (FCR, Page 0)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO trigger level, and selecting the DMA modes. Table 11 shows FCR bit settings.
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Table 11: FIFO Control Register Description
Bit 7:6 Symbol FCR[7:6] Description RX FIFO Trigger Level Select 00 : 8 characters (default) 01 : 16 characters 10 : 56 characters 11 : 60 characters 5:4 FCR[5:4] TX FIFO Trigger Level Select 00 : 8 characters (default) 01 : 16 characters 10 : 32 characters 11 : 56 characters FCR[5:4] can only be modified and enabled when EFR[4] is set. 3 FCR[3] DMA Mode Select 0 : Set DMA mode 0 (default) 1 : Set DMA mode 1 2 FCR[2] TX FIFO Reset 0 : No TX FIFO reset (default) 1 : Reset TX FIFO pointers and TX FIFO level counter logic. This bit will return to `0' after resetting FIFO. 1 FCR[1] RX FIFO Reset 0 : No RX FIFO reset (default) 1 : Reset RX FIFO pointers and RX FIFO level counter logic. This bit will return to `0' after resetting FIFO. 0 FCR[0] FIFO enable 0 : Disable the TX and RX FIFO (default). 1 : Enable the TX and RX FIFO
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7.6 Line Control Register (LCR, Page 0)
LCR controls the asynchronous data communication format. The word length, the number of stop bits, and the parity type are selected by writing the appropriate bits to the LCR. Table 12 shows LCR bit settings.
Table 12: Line Control Register Description
Bit 7 Symbol LCR[7] Description Divisor Latch Enable. 0 : Disable the divisor latch (default). 1 : Enable the divisor latch. 6 LCR[6] Break Enable. 0 : No TX break condition output (default). 1 : Forces TXD output to `0', for alerting the communication terminal to a line break condition. 5 LCR[5] Set Stick Parity. LCR[5:3] = xx0 : No parity is selected. LCR[5:3] = 0x1 : Stick parity disabled. (default) LCR[5:3] = 101 : Stick parity is forced to `1'. LCR[5:3] = 111 : Stick parity is forced to `0'. 4 LCR[4] Parity Type Select. LCR[5:3] =001 : Odd parity is selected. LCR[5:3] =011 : Even parity is selected. 3 LCR[3] Parity Enabled. 0 : No parity (default). 1 : A parity bit is generated during the transmission and the receiver checks for receive parity. 2 LCR[2] Number of Stop Bits. LCR[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8). LCR[2:0] = 100 : 1.5 stop bits (word length = 5). LCR[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8). 1:0 LCR[1:0] Word Length Bits. 00 : 5 bits (default). 01 : 6 bits. 10 : 7 bits. 11 : 8 bits.
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7.7 Modem Control Register (MCR, Page 0)
MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 13 shows MCR bit settings.
Table 13: Modem Control Register Description
Bit 7 Symbol MCR[7] Description Clock Prescaler Select. 0 : Divide by 1 clock input (default). 1 : Divide by 4 clock input. 6 MCR[6] Page 2 Select/Xoff Re-Transmit Access Enable 0 : Enable access to page 0 register when LCR[7] is `0' (default). 1 : Enable access to page 2 register and Xoff re-transmit bit when LCR[7] is `0'. 5 MCR[5] Xon Any Enable. 0 : Disable Xon any (default). 1 : Enable Xon any. 4 MCR[4] Internal Loop Back Enable. 0 : Disable loop back mode (default). 1 : Enable internal loop back mode. In this mode the MCR[3:0] signals are looped back into MSR[7:4] and TXD output is looped back to RXD input internally. 3 MCR[3] OUT2/Interrupt Output Enable. 0 : INTx outputs disabled (default). During loop back mode, OUT2 output `0' and it controls MSR[7] to `1'. 1 : INTx outputs enabled. During loop back mode, OUT2 output `1' and it controls MSR[7] to `0'. OUT2 is not available as an output pin on the SB16C1054. 2 MCR[2] OUT1/Xoff Re-transmit Enable. 0 : Xoff re-transmit disable when MCR[6] is `0'. During loop back mode, OUT1 output to `0' and it controls MSR[6] to `1'. 1 : Xoff re-transmit enable when MCR[6] is `1'. During loop back mode, OUT1 output to `1' and it controls MSR[6] to `0'. OUT1 is not available as an output pin on the SB16C1054. Xoff re-transmit is operated with XRCR, refer to XRCR. 1 MCR[1] RTS# Output. 0 : Force RTS# output to `1'. During loop back mode, controls MSR[4] to `1'. 1 : Force RTS# output to `0'. During loop back mode, controls MSR[4] to `0'. 0 MCR[0] DTR# Output. 0 : Force DTR# output to `1'. During loop back mode, controls MSR[5] to `1'. 1 : Force DTR# output to `0'. During loop back mode, controls MSR[5] to `0'.
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7.8 Line Status Register (LSR, Page 0)
LSR provides the status of data transfers between the UART and the CPU. When LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO. The errors in a character are identified by reading LSR and then reading RBR. Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RBR. Table 14 shows LSR bit settings.
Table 14: Line Status Register Description
Bit 7 Symbol LSR[7] Description RX FIFO data error Indicator. 0 : No RX FIFO error (default). 1 : At least one parity error, framing error, or break indication is in the RX FIFO. This bit is cleared when there is no more error in any of characters in the RX FIFO. 6 LSR[6] THR and TSR Empty Indicator. 0 : THR or TSR is not empty. 1 : THR and TSR are empty. 5 LSR[5] THR Empty Indicator. 0 : THR is not empty. 1 : THR is empty. It indicates that the UART is ready to accept a new character for transmission. In addition, it uses the UART to generate an interrupt to the CPU when the THR empty interrupt enable is set to `1'. 4 LSR[4] Break Interrupt Indicator. 0 : No break condition (default). 1 : The receiver received a break signal (RXD was `0' for at least one character frame time). In FIFO mode, only one character is loaded into the RX FIFO. 3 LSR[3] Framing Error Indicator. 0 : No framing error (default). 1 : Framing error. It indicates that the received character did not have a valid stop bit. 2 LSR[2] Parity Error Indicator. 0 : No parity error (default). 1 : Parity error. It indicates that the receive character did not have the correct even or odd parity, as selected by the LCR[4] 1 LSR[1] Overrun Error Indicator. 0 : No overrun error (default). 1 : Overrun error. It indicates that the character in the RBR or RX FIFO was not read by the CPU, thereby ignored the receiving character. 0 LSR[0] Receive Data Ready Indicator. 0 : No character in the RBR or RX FIFO. 1 : At least one character in the RBR or RX FIFO.
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7.9 Modem Status Register (MSR, Page 0)
MSR provides the current status of control signals from modem or auxiliary devices. MSR[3:0] are set to `1' when input from modem changes and cleared to `0' as soon as CPU reads MSR. Table 15 shows MSR bit settings.
Table 15: Modem Status Register Description
Bit 7 Symbol MSR[7] Description DCD Input Status. Complement of Data Carrier Detect (DCD#) input. In loop back mode this bit is equivalent to OUT2 in the MCR. 6 MSR[6] RI Input Status. Complement of Ring Indicator (RI#) input. In loop back mode this bit is equivalent to OUT1 in the MCR. 5 MSR[5] DSR Input Status. Complement of Data Set Ready (DSR#) input. In loop back mode this bit is equivalent to DTR in the MCR. 4 MSR[4] CTS Input Status. Complement of Clear To Send (CTS#) input. In loop back mode this bit is equivalent to RTS in the MCR. 3 MSR[3] DCD Input Status. 0 : No change on CD# input (default). 1 : Indicates that the DCD# input has changed state. 2 MSR[2] RI Input Status. 0 : No change on RI# input (default). 1 : Indicates that the RI# input has changed state from `0' to `1'. 1 MSR[1] DSR Input Status. 0 : No change on DSR# input (deault). 1 : Indicates that the DSR# input has changed state. 0 MSR[0] CTS Input Status. 0 : No change on CTS# input (deault). 1 : Indicates that the CTS# input has changed state.
7.10 Scratch Pad Register (SPR, Page 0)
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a scratch pad register to be used by the programmer to hold data temporarily.
7.11 Divisor Latches (DLL, DLH, Page 1)
Two 8-bit registers which store the 16-bit divisor for generation of the clock in baud rate generator. DLH stores the most significant part of the divisor, and DLL stores the least significant part of the divisor. Divisor of zero is not recommended. Note that DLL and DLH can only be written to before sleep mode is enabled, i.e., before IER[4] is set. Chapter 6.7 describes the details of divisor latches.
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7.12 Global Interrupt Control Register (GICR, Page 2)
GICR is a register that internal four 16C1050 UARTs share to use. It is used when determining whether each interrupt generated at four 16C1050 UARTs are transmitted to global interrupts or not. Table 16 shows the GICR bit settings.
Table 16: Global Interrupt Control Register Description
Bit 7:1 0 Symbol GICR[7:1] GICR[0] Description Not used, always `000_0000' Global Interrupt Mask. 0 : Deasserted, irrespective of occurring interrupts of four 16C1050 UARTs displayed on GISR[3:0]. `1' is outputted if global interrupt polarity, AFR[5] is `0' and outputted `0' if `1'. 1 : Generates interrupt when all the values of GISR[3:0] are not `0'. If all the values of GISR[3:0] are `0', interrupt is not outputted on GINT pin. `1' is outputted if AFR[5] is `0' and `0' is outputted if `1'.
7.13 Global Interrupt Status Register (GISR, Page 2)
GISR is a register that internal four 16C1050 UARTs share to use. It is used to verify the generation status of each interrupt of four 16C1050 UARTs when global interrupt function is enabled. Table 17 shows GISR bit settings.
Table 17: Global Interrupt Status Register Description
Bit 7 6:4 3 Symbol GISR[7] GISR[6:4] GISR[3] Description Mirror the content of GICR[0]. Not used, always `00'. UART of CS3# Interrupt Status. 0 : UART of CS3# interrupt was not generated. 1 : UART of CS3# interrupt was generated. 2 GISR[2] UART of CS2# Interrupt Status. 0 : UART of CS2# interrupt was not generated. 1 : UART of CS2# interrupt was generated. 1 GISR[1] UART of CS1# Interrupt Status. 0 : UART of CS1# interrupt was not generated. 1 : UART of CS1# interrupt was generated. 0 GISR[0] UART of CS0# Interrupt Status. 0 : UART of CS0# interrupt was not generated. 1 : UART of CS0# interrupt was generated.
7.14 Transmit FIFO Count Register (TCR, Page 2)
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TCR shows the number of characters that can be stored in TX FIFO. In 64-byte FIFO mode, it consists of only TCR[6:0]. If the number of characters that can be stored in TX FiFO is 0, it is shown as `0000_0000' and if 64, it is shown as `0100_0000'. In 256-byte FIFO mode, it consists of ISR[7] + TCR[7:0]. If the number of characters that can be stored in TX FiFO is 0, it is shown as `0_0000_0000' and if 255, it is shown as `0_1111_1111'. And in case of the maximum number 256, it is shown as `1_0000_0000'.
7.15 Receive FIFO Count Register (RCR, Page 2)
RCR shows the number of characters that is stored in RX FIFO. In 64-byte FIFO mode, it consists of only RCR[6:0]. If the number of characters that is stored in RX FiFO is 0, it is shown as `0000_0000' and if 64, it is shown as `0100_0000'. In 256-byte FIFO mode, it consists of ISR[6] + RCR[7:0]. If the number of characters that is stored in RX FiFO is 0, it is shown as `0_0000_0000' and if 255, it is shown as `0_1111_1111'. And in case of the maximum number 256, it is shown as `1_0000_0000'.
7.16 Flow Control Status Register (FSR, Page 2)
FSR show the status of operation of TX Hardware Flow Control, RX Hardware Flow Control, TX Software Flow Control, and RX Software Flow Control.
Table 18: Flow Control Status Register Description
Bit 7:6 5 Symbol FSR[7:6] FSR[5] Description Not used, always `00'. TX Hardware Flow Control Status. 0 : When FIFO or Auto-RTS flow control is disabled. If FIFO and Auto-RTS flow control is enabled, it means the number of data received in RX FIFO at the first time is less than the value of FUR, or it means the number of data in RX FIFO was more than the value of FUR and after the CPU read them, the number of data that remains unread is less than or equal to the value of FLR. That is, UART reports external device that it can receive more characters. 1 : It shows that the number of data received in RX FIFO exceeds the value of FUR and UART reports external device that it cannot receive more data. If RX FIFO has space to store more data, new data are stored in RX FIFO but after it gets full, they are lost. For more details, refer to `6.2 Hardware Flow Control'. 4 FSR[4] TX Software Flow Control Status. 0 : When FIFO or Software flow control is disabled. If FIFO and Software flow control is enabled, it means the number of data received in RX FIFO at the first time is less than the value of FUR, or it means the number of data in RX FIFO was more than the value of FUR and after the CPU read them, the number of data that remains unread after the CPU read the data received in RX FIFO is less than or equal to the value of FLR. That
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is, UART transmits Xon character to report external device that it can receive more data. 1 : It shows that the number of data received in RX FIFO exceeds the value of FUR and transmitting Xoff character to report external device that it cannot receive more data. If RX FIFO has space to store more data, new data are stored in RX FIFO but after it gets full, they are lost. For more details, refer to `6.3 Software Flow Control'. 3:2 1 FSR[3:2] FSR[1] Not used, always `00'. RX Hardware Flow Control Status. 0 : When FIFO or Auto-CTS flow control is disabled. If FIFO and Auto-CTS flow control is enabled, `0' is inputted in CTS# pin and it means external device can receive more data. This time data in TX FIFO are transmitted. 1 : If FIFO and Auto-CTS flow control is enabled, `1' is inputted in CTS# pin and it means external device can not receive more data. This time data in TX FIFO are not transmitted. For more details, refer to `6.2 Hardware Flow Control'. 0 FSR[0] RX Software Flow Control Status. 0 : When FIFO or RX Software flow control is disabled. If FIFO and RX Software flow control is enabled, it means Xoff character has never arrived or Xon character arrived after Xoff character had arrived(it means external device can receive more data). This time data in TX FIFO are transmitted. 1 : If FIFO and RX Software flow control is enabled, it means Xoff character has arrived and external device can not receive data any more. This time characters in TX FIFO are not transmitted. For more details, refer to `6.3 Software Flow Control'.
7.17 Page Select Register (PSR, Page 3)
If BFh is written in LCR, registers in Page3 and Page4 can be accessed. PSR is used to determine which page to use. Table 19 shows PSR bit settings.
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Table 19: Page Select Register Description
Bit 7:1 Symbol PSR[7:1] Description Access Key. When writing data on PSR to change page, Access Key must be correspondent. If the value of PSR[7:1] is `1010_010', data is written on PSR[0] and page can be selected. If PSR[7:1] is read, it reads `0000_000' which is irrespective of Access Key. 0 PSR[0] Page Select. 0 : Page 3 is selected (default). 1 : Page 4 is selected.
7.18 Auto Toggle Control Register (ATR, Page 3)
ATR controls the signals for controlling input/output signals when using Line Interface as RS422 or RS485, so eliminates additional glue logic outside. Table 20 shows ATR bit settings.
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Table 20: Auto Toggle Control Register Description
Bit 7 Symbol ATR[7] Description RXEN Polarity Select. 0 : Asserted output of RXEN is `0'. (default) 1 : Asserted output of RXEN is `1'. 6 ATR[6] RXEN Control Mode Select. 0 : RXEN is outputted as same as ATR[7], irrespective of TXD signal. (default) 1 : RXEN is outputted after making complement of ATR[7] when TXD signal is transmitting. And outputted as same as ATR[7] when TXD is not transmitting. 5 ATR[5] TXEN Polarity Select. 0 : Asserted output of TXEN is `0'. (default) 1 : Asserted output of TXEN is `1'. 4 ATR[4] TXEN Control Mode Select. Only when ATR[1:0] is `11'; 0 : TXEN is outputted as same as ATR[5], irrespective of TXD signal. (default) 1 : RXEN is outputted after making complement of ATR[5] when TXD signal is transmitting, and outputted after making complement of ATR[7] when TXD is not transmitting.. 3:2 1:0 ATR[3:2] ATR[1:0] Not used, always `00'. Auto Toggle Enable. 00 : Auto toggle is disabled (default). RTS#/TXEN, DTR#TXEN pin operate as RTS#, DTR#. If 80pin, each of TXRDY/TXEN, RXRDY/RXEN operates as TXRDY, RXRDY. 01 : RTS#/TXEN pin operates as TXEN. DTR#/TXEN pin operates as DTR#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN operates as TXRDY, RXRDY. 10 : DTR#/TXEN pin operates as TXEN. RTS#/TXEN operates as RTS#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN operates as TXRDY, RXRDY. 11 : Only in 80-pin. TXRDY/TXEN, RXRDY/RXEN pin operates as TXEN, RXEN. RTS#/TXEN, DTR#/TXEN operates as RTS#, DTR#.
7.19 Enhanced Feature Register (EFR, Page 3)
EFR enables or disables the enhanced features of the UART. Table 21 shows EFR bit settings.
Table 21: Enhanced Feature Register Description
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Bit 7 Symbol EFR[7] Description Auto-CTS Flow Control Enable. 0 : Auto-CTS flow control is disabled (default). 1 : Auto-CTS flow control is enabled. Transmission stops when CTS# pin is inputted `1'. Transmission resumes when CTS# pin is inputted `0'. 6 EFR[6] Auto-RTS Flow Control Enable. 0 : Auto-RTS flow control is disabled (default). 1 : Auto-RTS flow control is enabled. The RTS# pin outputs `1' when data in RX FIFO fill above the FUR. RTS# pin outputs `0' when data in RX FIFO fall below the FLR. 5 EFR[5] Special Character Detect. 0 : Special character detect disabled (default). 1 : Special character detect enabled. The UART compares each incoming character with data in Xoff2 register. If a match occurs, the received data is transferred to RX FIFO and ISR[4] is set to `1' to indicate that a special character has been detected. 4 EFR[4] Enhanced Function Bits Enable. 0 : Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]. 1 : Enables enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write enable. 3:0 EFR[3:0] Software Flow Control Select. Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. See Table 3 "Software flow control options (EFR[3:0])" on page 11.
7.23 Additional Feature Register (AFR, Page 4)
AFR enables or disables the 256-byte FIFO mode and controls the global interrupt. Table 22 shows AFR bit settings.
Table 22: Additional Feature Register Description
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Bit 7:6 5 Symbol AFR[7:6] AFR[5] Description Not used, always `00'. Global Interrupt Polarity Select 0 : GINT pin outputs `0' when interrupt is generated (default). 1 : GINT pin outputs `1' when interrupt is generated. 4 AFR[4] Global Interrupt Enable 0 : INT0/GINT pin is selected to INT0 (default). 1 : INT0/GINT pin is selected to GINT. 3:1 0 AFR[3:1] AFR[0] Not used, always `000'. 256-byte FIFO Enable. 0 : 256-byte FIFO mode is disabled and this means SB16C1054 operates as Non FIFO mode or 64-byte FIFO mode (default). 1 : 256-byte FIFO mode is enabled and ISR[7:6] operates as 256-TX FIFO Empty and 256-RX FIFO Full.
7.24 Xoff Re-transmit Count Register (XRCR, Page 4)
XRCR operates only when Software flow control is enabled by EFR[3:0] and Xoff Retransmit function of MCR[2] is also enabled. And it determines the period of retransmission of Xoff character. Table 23 shows XRCR bit settings.
Table 23: Xoff Re-transmit Count Register Description
Bit 7:2 1:0 Symbol XRCR[7:2] XRCR[1:0] Description Not used, always `0000_00'. Xoff Re-transmit Count Select 00 : Transmits Xoff character whenever the number of received data is 1 during XOFF status. (default) 01 : Transmits Xoff character whenever the number of received data is 4 during XOFF status. 10 : Transmits Xoff character whenever the number of received data is 8 during XOFF status. 11 : Transmits Xoff character whenever the number of received data is 16 during XOFF status.
7.25 Transmit FIFO Trigger Level Register (TTR, Page 4)
Operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte TX FIFO for generating transmit interrupt. Interrupt is generated when the number of data remained in TX FIFO after transmitting through TXD pin is less than the value of TTR. Initial value is 128h, `1000_0000' and `0000_0000' must not be written. If written, unexpected operation may occur.
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7.26 Receive FIFO Trigger Level Register (RTR, Page 4)
Operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte RX FIFO for generating receive interrupt. Interrupt is generated when the number of data remained in RX FIFO exceeds the value of RTR(this time, timeout or interrupt is valid). Initial value is 128h, `1000_0000' and `0000_0000' must not be written. If written, unexpected operation may occur.
7.27 Flow Control Upper Threshold Register (FUR, Page 4)
It can be written only when 256-byte FIFO mode is enabled and one of TX software flow control or Auto-RTS is enabled (In 64-byte mode, it cannot be written but can be read only, and follows the value of trigger level set in FCR[5:4]). While TX software flow control is enabled, Xoff character is transmitted when the number of data in RX FIFO exceeds the value of FUR. If Auto-RTS is enabled, `1' is outputted on RTS# pin to report that it cannot receive data any more. If both TX software flow control and Auto-RTS is enabled, Xoff character is transmitted and `1' is outputted on RTS# pin. The value of FUR must be larger than that of FLR.
7.28 Flow Control Lower Threshold Register (FLR, Page 4)
It can be written only when 256-byte FIFO mode is enabled and one of TX software flow control, or Auto-RTS is enabled (In 64-byte mode, it cannot be written but can be read only, and follows the value of trigger level set in FCR[7:6]). While TX software flow control is enabled, Xon character is transmitted when the number of data in RX FIFO is less than the value of FUR only if Xoff character is transmitted before. If Auto-RTS is enabled, `0' is outputted on RTS# pin to report that it can receive more data. If both TX software flow control and Auto-RTS is enabled, Xon character is transmitted only if Xoff character is transmitted before and `0' is outputted on RTS# pin. The value of FLR must be less than that of FUR.
Table 24: SB16C1054 Reset Conditions
Registers RBR IER FCR ISR Reset State Page 0 [7:0] = `XXXX_XXXX' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0001'
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LCR MCR LSR MSR SPR DLL DLM GICR GISR TCR RCR FSR PSR ATR EFR XON1 XON2 XOFF1 XOFF2 AFR XRCR TTR RTR FUR FLR Output Signals TXD, RTS#, DTR# TXRDY# RXRDY# INT [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0110_0000' [7:4] = `0000' [3:0] = Logic levels of the inputs inverted [7:0] = `0000_0000' Page 1 [7:0] = `1111_1111' [7:0] = `1111_1111' Page 2 [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' Page 3 [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' Page 4 [7:0] = `0000_0000' [7:0] = `0000_0000' [7:0] = `1000_0000' [7:0] = `1000_0000' [7:0] = `0000_0000' [7:0] = `0000_0000' Reset State Logic 1 Logic 0 Logic 1 Tri-State Condition = INTSEL is open or low state Logic 0 = INTSEL is high state
8. Programmer's Guide
The base set of registers that is used during high-speed data transfer has a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access. Some streamlining through interleaving can be obtained when programming all the registers.
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IN16C1054
Table 25: Register Programming Guide
Command Set Baud Rate to VALUE1, VALUE2 Action Read LCR, save in temp Set LCR to 80h Set DLL to VALUE1 Set DLM to VALUE2 Set LCR to temp Set Xon1, Xoff1 to VALUE1, VALUE2 Read LCR, save in temp Set LCR to BFh Set Xon1 to VALUE1 Set Xoff1 to VALUE2 Set LCR to temp Set Xon2, Xoff2 to VALUE1, VALUE2 Read LCR, save in temp Set LCR to BFh Set Xon2 to VALUE1 Set Xoff2 to VALUE2 Set LCR to temp Set Software Flow Control Mode to VALUE Read LCR, save in temp Set LCR to BFh Set EFR to VALUE Set LCR to temp Set flow control threshold for 64-byte FIFO Mode 1) Set FCR to `0000_xxx1' Set FUR to 8, set FLR to 0 2) Set FCR to `0101_xxx1' Set FUR to 16, set FLR to 8 3) Set FCR to `1010_xxx1' Set FUR to 56, set FLR to 16 4) Set FCR to `1111_xxx1' Set FUR to 60, set FLR to 56 Set flow control threshold for 256-byte FIFO Mode Set FCR to `xxxx_xxx1' Read LCR, save in temp Set LCR to BFh Set PSR to A5h Set AFR to 01h
Table 25: Register Programming Guide...continued
Command Action Set FUR to Upper Threshold Value Set FLR to Lower Threshold Value Set PSR to A4h Set LCR to temp Set TX FIFO / RX FIFO Interrupt Trigger Level for 64-byte FIFO Mode 1) Set FCR to `0000_xxx1' Set RTR to 8, set TTR to 8 2) Set FCR to `0101_xxx1'
Rev. 00
IN16C1054
Set RTR to 16, set TTR to 16 3) Set FCR to `1010_xxx1' Set RTR to 56, set TTR to 32 4) Set FCR to `1111_xxx1' Set RTR to 60, set TTR to 56 Set TX FIFO / RX FIFO Interrupt Trigger Level for 256-byte FIFO Mode Set FCR to `xxxx_xxx1' Read LCR, save in temp Set LCR to BFh Set PSR to A5h Set AFR to 01h Set TTR to TX FIFO Trigger Level Value Set RTR to RX FIFO Trigger Level Value Set PSR to A4h Set LCR to temp Read Flow Control Status Read LCR, save in temp1 Read MCR, save in temp2 Set LCR to (`0111_1111' AND temp1) Set MCR to (`0100_0000' OR temp2) Read FSR, save in temp3 Pass temp3 back to host Set MCR to temp2 Set LCR to temp1 Read TX FIFO / RX FIFO Count Value Read LCR, save in temp1 Read MCR, save in temp2 Set LCR to (`0111_1111' AND temp1) Set MCR to (`0100_0000' OR temp2) Read TCR, save in temp3 Read RCR, save in temp4 Pass temp3 back to host Pass temp4 back to host Set MCR to temp2 Set LCR to temp1
Table 25: Register Programming Guide...continued
Command Read 256-byte TX FIFO Empty Status / RX FIFO Full Status Action Set FCR to `xxxx_xxx1' Read LCR, save in temp1 Set LCR to BFh Set PSR to A5h Set AFR to 01h Set PSR to A4h Set LCR to temp1 Read ISR, save in temp2
Rev. 00
IN16C1054
Pass temp2 back to host Enable Xoff Re-transmit Read LCR, save in temp1 Set LCR to not BFh Read MCR, save in temp2 Set MCR to (`0100_0000' OR temp2) Set MCR to (`0100_0100' OR temp2) Set MCR to (`1011_1111' AND temp2) Set MCR to temp2 Set LCR to temp1 Disable Xoff Re-transmit Read LCR, save in temp1 Set LCR to not BFh Read MCR, save in temp2 Set MCR to (`0100_0000' OR temp2) Set MCR to (`1011_1011' AND temp2) Set MCR to temp2 Set LCR to temp1 Set Prescaler Value to Divide-by-1 or 4 Read LCR, save in temp1 Set LCR to BFh Read EFR, save in temp2 Set EFR to (`0001_0000' OR temp2) Set LCR to 00h Read MCR, save in temp3 if Divide-by-1 = OK then Set MCR to (`0111_1111' AND temp3) else Set MCR to (`1000_0000' OR temp3) Set LCR to BFh Set EFR to temp2 Set LCR to temp1
9. Electrical Characteristics
Absolute Maximum Ratings
Symbol VCC VI VO Tamb Tstg Parameter Supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature In free-air Conditions Min -- -- 0.5 GND + 0.1 -- 40 -- 60 Max 3.6 5.5 VCC - 0.1 +85 +150 Unit V V V
Rev. 00
IN16C1054
DC Electrical Characteristics
Symbol VCC VI VIH VIL VO VOH VOL CI Parameter Supply voltage Input voltage High-level input voltage Low-level input voltage Output voltage High-level output voltage Low-level output voltage Input capacitance Oscillator/Clock speed Clock duty cycle ICC ICCsleep Supply current Sleep current IOH = -- 8mA IOL = 8mA Conditions Min 2.7 0 VCC 0.7 0 0 2.4 -- -- -- -- -- -- 3.3 -- -- -- -- -- -- -- -- 50 -- -- 3.3V Nom Max 3.6 VCC
5.5
Unit V V V V V V V pF MHz % mA mA
VCC 0.3 VCC -- 0.4 9 85 --
Symbol
Parameter Pulse duration, IOR# low Set up time, CSx# valid before IOR# low Set up time, A2~A0 valid before IOR# low Hold time, A2~A0 valid after IOR# high Hold time, CSx# valid after IOR# high Delay time, tar+trd+trc Delay time, IOR# high to IOR# or IOW# low Pulse duration, IOW# Setup time, CSx# valid before IOW# Setup time, A2~A0 valid before IOW#
Min 24 10 10 2 0 54 20 24 10 10
Max
Unit ns ns ns ns ns ns ns ns ns ns
trd tcsr tar tra trcs tfrc trc twr tcsw taw
Rev. 00
IN16C1054
tds twa twcs tdh tfwc twc trvd thz tirs tsti tsi tsxa thr tir twxi tsint trint trint tmdo tsim trim tsim
Setup time, D7~D0 valid before IOW# Hold time, A2~A0 valid after IOW# Hold time, CSx# valid after IOW# Hold time, D7~D0 valid after IOW# Delay time, taw+twr+twc Delay time, IOW# to IOW# or IOR# Enable time, IOR# to D7~D0 valid Disable time, IOR# to D7~D0 released Delay time, INTx to TXDx at start Delay time, TXDx at start to INTx Delay time, IOW# high or low (WR THR) to INTx Delay time, TXDx at start to TXRDY# Propagation delay time, IOW#(WR THR) to INTx Propagation delay time, IOR#(RD IIR) to INTx Propagation delay time, IOW#(WR THR) to TXRDY# Delay time, stop bit to INTx or stop bit to RXRDY# or read RBR to set interrupt Propagation delay time, Read RBR/LSR to INTx/LSR interrupt Propagation delay time, IOR# RCLK to RXRDY# Propagation delay time, IOW#(WR MCR) to RTSx#, DTRx# Propagation delay time, modem input CTSx#, DSRx#, and DCDx# to INTx Propagation delay time, IOR#(RD MSR) to interrupt Propagation delay time, Rix# to INTx# 1 12 12 12 12 3 12 4 8 8 16 24 8 32 8 12 12 10 15 2 2 5 54 20 24 ns ns ns ns ns ns ns ns RCLK RCLK RCLK RCLK ns ns ns RCLK ns ns ns ns ns ns
The internal address strobe is always in active state. In the FIFO mode, td1= xxns (min) between reads of the FIFO and the status register.
Rev. 00
IN16C1054
A[2:0]
VALID ADDRESS t ra
CSx#
t csr t ar t frc t rcs
IOR#
t rd t rc
ACTIVE
IOW#
t rvd t hz VALID DATA
D[7:0]
Figure 10: Read Cycle Timing
A[2:0]
VALID ADDRESS t wa
CSx#
t csw t aw t fwc t wcs
IOR#
t wr t wc ACTIVE t ds t dh
IOW#
D[7:0]
VALID DATA
Figure 11: Write Cycle Timing
Rev. 00
IN16C1054
TXDx
START
DATA(5-8)
PARITY
STOP(1-2)
START
t irs
t sti
INTx
t hr t si t hr
IOW# (WR THR)
t ir
IOR# (RD IIR)
Figure 12: Transmitter Timing
IOW# (WR THR)
BY TE #1
TXDx
DATA
PARITY
STOP
START
TXRDY#
t w xi t sxa
Figure 13: Transmitter Ready Mode 0 Timing
IOW# (WR THR)
BY TE #16
TXDx
DATA
PARITY
STOP
START
TXRDY#
t w xi
FIFO FULL
t sxa
Figure 14: Transmitter Ready Mode 1 Timing
Rev. 00
IN16C1054
RXDx Sample Clock INTx(TRIGGER LEVEL INTERRUPT (FCR6, 7 = 0, 0)
START
DATA(5-8)
PARITY
STOP
(FIFO AT OR ABOVE TRIGGER LEVEL)
t sint t rint
(FIFO BELOW TRIGGER LEVEL)
LSI INTERRUPT IOR# (RD LSR)
t rint
IOR# (RD RBR)
Figure 15: Receiver FIFO First Byte (Sets RBR) Timing
RXDx Sample Clock TIMEOUT OR TRIGGER LEVEL INTERRUPT
STOP
(FIFO AT OR ABOVE TRIGGER LEVEL)
t sint t rint
(FIFO BELOW TRIGGER LEVEL)
LSI INTERRUPT IOR# (RD LSR)
TOP BYTE OF FIFO
t sint t rint
IOR# (RD RBR) PREVIOUS BYTE READ FROM FIFO
Figure 16: Receiver FIFO After First Byte (After RBR Set) Timing
Rev. 00
IN16C1054
IOR# (RD RBR)
RXDx (FIRST BYTE) Sample Clock
STOP
RXRDY#
t sint t rint
Figure 17: Receiver Ready Mode 0 Timing
IOR# (RD RBR) RXDx (FIRST BYTE THAT REACHES THE TRIGGER LEVEL) Sample Clock
STOP
RXRDY#
t sint t rint
Figure 18: Receiver Ready Mode 1 Timing
IOW# (WR MCR)
t mdo t mdo
RTSx#, DTRx#
CTSx#, DSRx#, DCDx#
INTx
t sim t rim t sim t rim t sim
IOR# (RD MSR)
RIx#
Figure 19: Modem Control Timing
Rev. 00
IN16C1054
10. Package Outline
80-Pin TQFP: Thin Plastic Quad Flat Package; Body 12 12 1.0 mm
0,50
0,27 0,17
1,20 MAX
9,50 12,00 14,00 1,05 0,95 1.00
0,10 0,75 0,45
0-7
Note :
1. All dimensions are in millimeters. 2. Falls within ANSI Y14.5-1982
68-Pin PLCC: Plastic Leaded Chip Carrier
Rev. 00
IN16C1054
0.995 (25,273) 0.985 (25,019) 0.032 (0.081) 0.026 (0,66) 0.956 (24,282) 0.950 (24,130)
0.18 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.02 (0,51) MIN
0.995 (25,273) 0.985 (25,019)
0.956 (24,282) 0.950 (24,130)
0.050 (1,27)
Note :
1. All dimensions are in inches (millimeters). 2. Falls within ANSI Y14.5-1982
0.021 (0,53) 0.013 (0,33)
0.469 (11,913) 0.441 (11,201)
0.469 (11,913) 0.441 (11,201)
Rev. 00

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